About Me
I am on the job market, looking for full-time industry research positions in Summer 2026. If you see a good fit and are interested in hiring, please reach out via email.
I am a final year PhD student in the Electrical Engineering and Computer Science (EECS) department at Massachusetts Institute of Technology (MIT). I am fortunate to have Prof. Anantha Chandrakasan and Prof. Hae-Seung Lee as my PhD advisors. I have been awarded the Grass Instrument Company Fellowship and the MathWorks Engineering Fellowship.
My research interests lie broadly in creating energy-efficient accelerators for AI and, in turn, utilizing GenAI for chip design, be it in circuit generation, sizing optimization, verification or performance prediction. I believe that by creating better chips for AI, we enable more powerful and efficient models, which will support the development of the next generation of chips.
I graduated with a B.Tech and an M.Tech in Electrical Engineering from IIT Bombay, where I was awarded the Sharad Maloo Memorial Gold Medal for being the second-most outstanding student among all B.Tech/Dual Degree graduating students (1 in 999) at the 59th Convocation of IIT Bombay.
In Summer 2025, I interned at NVIDIA Research as part of the ASIC and VLSI Research (AVR) group on using LLMs for RTL verification. Previously, I have interned at Qualcomm (Summer 2023) and TU Delft (Summer 2019).
Updates
| Nov 2025: | Gave a talk at MIT Center for Integrated Circuits and Systems on "AI-driven Automation for Analog Circuit Design" |
| Jul 2025: | Our work "Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input" accepted to IEEE Transactions on Circuits and Systems I: Regular Papers [paper] |
| Jun 2025: | Our work considered as a candidate for best paper! [paper] |
| Jun 2025: | Presented our work "LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits" at IEEE International Conference on LLM-Aided Design (ICLAD) [paper] |
| Jun 2025: | Filed a patent application with IBM for "Design Space Reduction and Optimization for Analog Circuits," U.S. App. No. 19/247,091, 2025. |
| Jun 2025: | Presented our work "LEDRO: LLM-Enhanced Design Space Reduction and Optimization for Analog Circuits" at the WIP poster session at Design Automation Conference (DAC) [paper] |
| Jun 2025: | Summer Internship at NVIDIA Research, in the ASIC and VLSI Research group on using LLMs for RTL Verification |
| May 2025: | Selected as a DAC Young Fellow 2025 |
| May 2025: | Completed Minor in Finance |
| May 2025: | Awarded MathWorks Engineering Fellowship for 2025-26 |
| May 2025: | Submitted my PhD thesis proposal on Artificial Intelligence-Driven Automation for Analog Circuit Design |
| May 2025: | Awarded Best Track Manuscript at IEEE International Symposium on Circuits and Systems (ISCAS) [paper] |
| May 2025: | Presented our work "Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input" at IEEE International Symposium on Circuits and Systems (ISCAS) [paper] |
| Feb 2025: | Completed my RQE (Research Qualifying Examination) |
| Jan 2025: | Presented our work "A 0.75mm2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices" at International Conference on VLSI Design and International Conference on Embedded Systems (VLSID) [paper] |
| Feb 2024: | Selected as TA for 6.6000 (6.775), CMOS Analog and Mixed-Signal Circuit Design |
| Jan 2024: | Filed a patent application for work done at Qualcomm, "Compute-in-Memory with Current Transition Detection," U.S. App. No. 18/403,010, 2024. [Patent app.] |
| Dec 2023: | Second tape-out in TSMC 28nm! |
| Oct 2023: | Selected as Mentor for Graduate Application Assistance Program, EECS, MIT |
| May 2023: | Summer Internship at Qualcomm, in the Memory-IP group on reliable in-memory computing |
| Sep 2022: | First tape-out in 14nm! |
| Dec 2021: | Joined the Energy-Efficient Circuits and Systems group, advised by Prof. Anantha Chandrakasan |
| Sep 2021: | Joined the PhD program at EECS, MIT; Awarded Grass Instrument Company Fellowship |
| Aug 2021: | Awarded the Sharad Maloo Memorial Gold Medal for being the second-most outstanding student in terms of general proficiency, excellence in academic performance, extracurricular activities, and social services among all B.Tech/Dual Degree graduating students (1 in 999) at the 59th Convocation of IIT Bombay |
| Aug 2021: | Graduated from IIT Bombay with a BTech in Electrical Engineering, minored in computer science, MTech in Electrical Engineering specializing in Microelectronics |
| May 2021: | Presented our work "Estimation of Time to Failure Distribution in SRAM due to Trapped Oxide Charges" at IEEE International Symposium on Circuits and Systems (ISCAS) [paper] |
| Apr 2021: | Awarded the ‘Travel Grants for UG students by C'1992 and C'1998’ for IEEE ISCAS 2021 |
| Mar 2021: | Presented our work "Modeling of HKMG Stack Process Impact on Gate Leakage, SILC and PBTI" at IEEE International Reliability Physics Symposium (IRPS) [paper] |
| Jan 2021: | Selected as TA for Control Systems (EE302) |
| Dec 2020: | Our work "A physical model for bulk gate insulator trap generation during bias-temperature stress in differently processed p-channel FETs" accepted to IEEE Transactions on Electron Devices [paper] |
| Jul 2020: | Selected as TA for Probability and Random Processes (EE325) |
| May 2020: | Summer Research in developing Stress Induced Leakage Current (SILC) framework |
| May 2019: | Summer Internship at Kavli Institute of Nanoscience, TU Delft on "Dipole-Exchange Spin Waves in Thin Ferromagnetic Films" |
| Apr 2019: | Awarded IITB Institute Journalism Special Mention Award |
| Mar 2019: | Stood in the top 5 teams in the Make in India presentation organised for TEQIP-III for heart rate variability analysis by processing the ECG signal & PSD to predict risk of myocardial infarction |
| Mar 2019: | Selected as Department Academic Mentor |
| May 2018: | Summer Research in developing Time Dependent Dielectric Breakdown (TDDB) framework |
| May 2018: | Awarded the best project among 70+ projects for implementing an audio volume controller, motion tracker & a pattern lock by gesture detection using infrared emitters & sensors |
| Apr 2018: | Awarded Hostel Cultural Color Award for contribution to film-making |
| Mar 2018: | Selected as Editor for Insight 2018-19, official student media body |
| Feb 2018: | Selected as TA for Differential Equations (MA108) |
| Jul 2017: | Selected as TA for Quantum Mechanics (PH107) |
| Mar 2017: | Selected as Convenor for IIT-BBC 2017-18 (IIT Bombay Broadcasting Channel), official student multimedia body |
| Nov 2016: | First Runner up in Segreta, the biggest Online Crypt Hunt, Techfest '16 among 6,000+ participants |
| Oct 2016: | Awarded Desai-Sethi Scholarship (Rs. 150K/year for 4 years awarded to top 5 girls admitted to IIT Bombay) |
| Jul 2016: | Joined IIT Bombay |
| Jun 2016: | Achieved All India Rank 102 in JEE Main and All India Rank 295 in JEE Advanced out of 1.2 and 0.2 million candidates respectively; stood first in both in the state of Maharashtra among girls |