Research
Low Power, Low Memory, General Purpose Accelerator for TinyML [May '22 - Present]
Advisor: Prof. Anantha Chandrakasan, Electrical Engineering and Computer Science, MIT
The growth in low-power, small area, embedded devices and advancement in the optimization of ML algorithms has resulted in tiny machine learning (TinyML), which calls for implementing the ML algorithm within the IoT device. TinyML is implemented through efficient hardware-software co-design. In this project, the aim is to design an accelerator which is optimized for area (low memory) and power while supporting a multitude of applications like voice activation, ECG, keyword spotting, visual wake word, pupil detection, time series, accelerometer, etc.- Designing a fused layer computation flow, with a light cryptographic engine for security
- Targeting total memory of 20kB (excluding input and output), with weight storage on chip, at near threshold voltage
- Motivated by the idea of an energy harvesting chip, have quantization as a function of energy
HKMG Stack Process Impact on Gate Leakage, SILC and PBTI [Dec '18 - Oct '20] [Paper] [Presentation]
Advisor: Prof. Souvik Mahapatra, Electrical Engineering , IIT Bombay
Stress Induced Leakage Current (SILC) and Bias Temperature Instability (BTI) remained as the forerunner in the device reliability domain with the continuous transistor scaling; PBTI remains a concern for N-MOSFETs. Bulk trap generation in HK for PBTI stress is estimated from SILC measurements. Recently, RD and RDD models are used for NBTI interface and bulk trap generation in PMOS.* This project aims to model direct tunneling leakage, SILC and PBTI along with the bulk traps generated and PBTI trap generation at IL/HK interface in NMOS with deeply scaled (down to EOT∼7Å) HKMG stacks.- Quantified impact of IL and HK thickness, channel/IL and IL/HK barriers on gate leakage and SILC
- Extracted bulk trap densities (ΔNOT) from SILC measurements of 7 differently processed HKMG NMOS using a Wentzel–Kramers–Brillouin (WKB) tunneling model and used a Reaction-Diffusion-Drift (RDD) framework to model them
- Modelled the traps generated from PBTI stress (ΔNIT) from DCIV measurements using the double interface H/H2 Reaction-Diffusion model
- Analysed impact of gate stack process (pre-clean, IL, IL/HK interface, HK and post-HK nitridation) on gate leakage, SILC and PBTI trap generation at IL/HK interface
Time to Failure Distribution of a Stored Bit in SRAM due to RTN [Dec '18 - Nov '20] [Paper] [Presentation]
Advisor: Prof. Animesh Kumar, Electrical Engineering , IIT Bombay
Trapping and detrapping of charges in the oxide interface of a MOSFET leads to a random telegraphic noise (RTN) injection and this phenomenon negatively affects the reliability of circuits. The objective of this project is to develop a reproducible strategy to obtain TTF distribution and related statistics for an SRAM cell of any technology with any given RTN model.- Proposed a method to estimate TTF distribution of a stored bit in an SRAM cell due to single or multi-level RTN by composition of Monte-Carlo simulations and circuit-level abstraction
- Showcased results of this procedure on an SRAM cell made from 45 nm technology with a single- trap RTN model at various supply voltages using Cadence, Ocean and Python scripting
- Indicated via circuit-level simulations that the TTF distribution worsens due to process variations
Dipole-Exchange Spin Waves for Thin Ferromagnetic Films [May '19 - Jul '19] [Presentation]
Advisors: Prof. Gerrit Bauer, Kavli Institute of Nanoscience, Applied Sciences, TU Delft
Prof. Yaroslav Blanter, Kavli Institute of Nanoscience, Applied Sciences, TU Delft
Surface spin waves (dipole) are chiral and exist only in thick magnetic films with small group velocities. Exchange waves are non chiral with high velocities at higher frequencies. Dipole-exchange spin waves exist in the middle of these two ends of wave vector range. Dispersion characteristics of spin waves in ferromagnetic films taking into account both the dipole-dipole and the exchange interactions are obtained by a sixth-order differential equation. The objective of this project is to solve it considering pinned and unpinned boundary conditions and study their variation with thickness in this transition region.- Calculated the wave function, magnetization and dipolar field profiles for various modes of spin waves for given film thickness by solving Landau–Lifshitz and Maxwells’ equations and appropriate boundary conditions
- Showed how chirality changes with thickness; obtained the dispersion relation (ω vs k⃗) for a film
- Obtained isofrequency curves and showed their change with increase in magnetic field in k⃗ space
- Model for Time Dependent Dielectric Breakdown (TDDB) for ultrathin oxides [May '18 - Jun '21] [Presentation]
Advisor: Prof. Souvik Mahapatra, Electrical Engineering , IIT Bombay
TDDB is a failure mechanism in MOSFETs, when the gate oxide breaks down as a result of long-time application of relatively low electric field. Time-dependent dielectric breakdown (TDDB) follows the Weibull distribution and is characterized by β, the Weibull slope. In this project, the change in the slope is explained by a percolation model with different defect generation rates in the bulk and channel/oxide and gate/oxide interfaces, also considering SILC slope and trap size changes with thickness. The model is then extended for high-k with interfacial SiO2.- Constructed a cell based MOSFET percolation model which generates bulk and interface traps with varied defect generation rates and procured the time at which a percolation path emerges using Breadth First Search (BFS) algorithm in C++
- Obtained time to failure distribution and analysed the relation of its Weibull slope with oxide thickness and obtained results obeying empirical claims and experimental data; verified area scaling
- Extending the model to a bilayer stack and including the effect of PBTI generated interface traps