Projects

1. Ring Oscillator Characterization across Stages and Transistor Size - Digital Circuits [Sep '22 - Oct '22]
   Advisors: Prof. Anantha Chandrakasan, EECS, MIT and Xin Zhang, IBM
   Taped out in 14nm FinFET Samsung technology, ring oscillators of different stages and transistor sizes, each with its own power line for accurate power management and frequency

2. Sub-100nm Gate GaN HEMT transistor fabrication - Device Fabrication [Sep '21 - Dec '21]
   Advisor: Prof. Tomas Palacios, EECS, MIT
   Fabricated a HEMT on GaN-on-Si with an I_ON = 1.3A/mm and R_ON = 1.54 Ohm at MIT.nano

3. Physically Unclonable Function (PUF) Circuit Design- Circuits [Oct '21 - Dec '21]
   Advisor: Prof. Anantha Chandrakasan, EECS, MIT
   Implemented latch-based and ring oscillator PUFs in TSMC 65nm technology

4. Low Power FC-CS CMOS Operational Amplifier - Analog Circuits [Mar '22 - Apr '22]
   Advisor: Prof. Harry Lee, EECS, MIT
   Designed an FC-CS CMOS opamp in 22nm bsim4 with power $<$ 1.5mW, settling times $<$ 8ns, open loop gain $>$ 10k, thermal noise $<$ 300uV, phase margin $>$ 65$^o$ at gain-of-2 frequency [Report]

5. Power Amplifier Design - Solid State Microwave Devices [Jan '19 - Apr '19]
   Advisor: Prof. Jayanta Mukherjee, EE, IITB
   Fabricated a power amplifier on FR4 substrate of gain 2.5 dB at 520 MHz with S₁₁ & S₁₂ values of -18 dB & -35 dB. Constructed matching networks for the given amplifier IC AFIC901N with appropriate bias tees at source & load, considering gain & stability of the circuit, using microstrip transmission lines. [Report] [files]

6. 4 X 4 Butler Matrix Circuit - Microwave Integrated Circuits [Sep '19 - Nov '19]
   Advisor: Prof. Jayanta Mukherjee, EE, IITB
   Fabricated on FR4 substrate using microstrip transmission lines and obtained equal power division and input port isolation. Constructed the circuit with 90 ° hybrids & phase delay lines using ideal T lines to equally divide power at the output ports for each of the 4 input ports at an operation frequency of 5.4 GHz. Redesigned it using microstrip transmission lines, and obtained accurate results after EM simulation of the layout. [Report] [files]

7. Layout and Back-extraction of 16 bit Brent Kung Adder - VLSI Design [Sep '19 - Nov '19]
   Advisor: Prof. Dinesh Sharma, EE, IITB
   Started from the schematic & layout of basic CMOS logic gates to build increasingly complex modules; combined them accordingly to obtain the layout of 16 bit Brent Kung adder in Cadence. Passed the Design Rule Checking (DRC) & Layout Versus Schematic (LVS), and did Parasitic Extraction (PEX) of each module of adder & the final adder. Conducted post layout simulation tests and successfully obtained accurate adder functionality. [Report] [files]

8. Pipelined RISC Microprocessor - Microprocessors [Jul '18 - Nov '18]
   Advisor: Prof. Virendra Singh, EE, IITB
   Designed IITB-RISC, an 8-register, 16-bit computer system which follows the standard 6 stage pipelines (Instruction fetch, instruction decode, register read, execute, memory access, and write back) capable of executing 15 instructions and equipped it with control flow, data forwarding, data dependency hazard detection and hazard mitigation. Implemented the design in VHDL, simulated it and tested it on a DE0-Nano FPGA board. [files]

9. Dot-Product Accelerator & Processor in Aa - Algorithmic Digital System Design [Jul '19 - Nov '19]
   Advisor: Prof. Madhav Desai, EE, IITB
   Learnt Algorithm assembly (Aa), a control-flow description language developed by the advisor. Implemented an accelerator in Aa for parallel dot product of a data matrix with a kernel matrix. Coded and verified a processor with given ISA in Aa, converted it to VHDL using AHIR tools, and tested it on a Basys-3 FPGA using Xilinx Vivado and communicated with it using UART. [files]

10. Music Genre Identification - Machine Learning [Feb '18 - May '18]
    Advisor: Prof. Preethi Jyothi, CSE, IITB
    Perused literature to find that the timbre feature corresponding to the loudest parts of the song gives better clustering of audio samples and implemented Principal Component Analysis (PCA) to show it. Utilized Bayesian Optimization for tuning of hyperparameters to compute posterior probability loss; utilized Gini Index for splitting at each node in Random Forests. Achieved an accuracy of 56% and an F1 score of 50.65% using the Random Forest algorithm. [Report] [files]

11. Magnon Spin Transport in Permalloy Modelling and Simulation - Numerical Modeling and Simulation [Sep '21 - Dec '21]
    Advisor: Prof. Luca Daniel, EECS, MIT
    Modelled the spin transport & spin leakage using spin resistors, the spin accumulation using a spin capacitor, and then constructed a tractable circuit diagram, using GCR for steady state [Report] [slides]

12. Monitoring Honking Rate to reduce Noise Pollution - Electronic Design [Jan '19 - May '19]
    Wadhwani Lab, EE, IITB
    Built a device to count a specific vehicle’s honks by an amplitude-frequency threshold circuit amid all the traffic noise, which can be calibrated before for the specific vehicle's horn. Transmitted this data to a server using ESP8266 wirelessly and provided for detection if the device is tampered with to hide honk count; can be used to monitor honking rate of a driver by authorities and take action. [Presentation] [Report]

13. Heart Rate Variability (HRV) Analysis- Digital Signal Processing [Feb '19 - Mar '19]
    Advisor: Prof. Vikram Gadre, EE, IITB
    Stood among the top 5 teams in the Make in India presentation organised for Technical Education Quality Improvement Programme (TEQIP)-III. Acquired, filtered, thresholded and interpolated the signal to obtain the HRV signal; extracted its power spectral density in MATLAB to make a model to predict the risk of myocardial infraction, in a team of 3. Presented to students and teachers of various tier 2 and 3 colleges across the country as part of TEQIP-KIT-2019 workshop under the initiative of the Ministry of Human Resource Development (MHRD), Government of India. [Presentation] [files]

14. Touchless Gesture Recognition - Analog Circuits [Feb '18 - Apr '18]
    Advisor: Prof. Siddharth Tallur, EE, IITB
    Part of a 2 member team that was awarded the best project among 70 teams. Designed and implemented a touchless gesture audio volume controller, motion tracker (using an LED matrix) and a pattern lock by gesture detection using infrared emitters and sensors. Implemented the digital logic on an Altera CPLD by coding in VHDL on Altera Quartus software. [Presentation] [files]

Other EE reports and projects:

• Multicycle Processor [Jul '18 - Nov '18)]
  Guide: Prof. Virendra Singh, EE, IITB
  Implemented a 16-bit computer system with 15 instructions in the Instruction Set Architecture in VHDL and optimized the architecture for performance using point-to-point communication infrastructure [files]

• Simulations of Microelectronics [Jul '19 - Nov '19]
  Guide: Prof. Swaroop Ganguly, EE, IITB
  Solved Poisson equation using finite difference scheme and Newton Raphson to obtain electric field, charge, etc. for various device structures. Used TCAD Sentaurus for sprocess simulations of implant and sdevice simulations for effect of various recombinations. [files]

• MOS Simulations [Jan '19 - Apr '19]
  Guide: Prof. Souvik Mahapatra, EE, IITB
  Simulated substrate charge, band bending, CV curves, effect of interface traps while checking variation with thickness and doping density, and Pao Sah, Brews models using MATLAB [files]

• Solving the generalized Sylvester’s equation AXB + CXD = E [Mar '20 - May '20]
  Guide: Prof. Virendra Sule, EE, IITB
  Studied various methods in literature and its implementation complexity in today's software. [Report]

• SAT solver [Oct '19 - Nov '19]
  Guide: Prof. Virendra Singh, EE, IITB
  On entering clauses in product of sum form, outputs whether SAT or UNSAT; if SAT provides a solution [files]

• Filter Design [Jan '19 - Apr '19]
  Guide: Prof. V. M. Gadre, EE, IITB
  Built discrete time IIR band pass and band stop filters using Chebyshev and Butterworth approximations respectively with the specifications stated and constructed corresponding FIR filters with the same specifications with Kaiser window using MATLAB [Report]

• Reaction Game [Mar '18 - May '18]
  Guide: Prof. Madhav Desai, EE, IITB
  Coded various components like a Linear-Feedback Shift Register (LFSR), Finite State Machines (FSMs) and an LCD control module for display using Register Transfer Level (RTL) abstractiona and implemented it on the Altera MAX3000A Complex Programmable Logic Device (CPLD) using Quartus [files]